Design of Reconfigurable Logic Controllers

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North Holland , , pp. Springer, London, Saul, E. Dagless: Petri net based algorithms for parallel controller synthesis. Dagless: Parallel controller synthesis from a Petri net specification. Billington, S. Christensen, K. Kindler, O. Kummer, L. Petrucci, R. Post, C. Stehno, M. Bubacz, M.

Adamski, Heuristic algorithm for an effective state encoding for reconfigurable matrix-based logic controller design. Chang, W. Kwon, J. Park: Hardware implementation of real time Petri-net-based controllers. Control Engineering Practice, , Vol. Cortadella, A. Yakovlev, G. Rozenberg: Concurrency and Hardware Design. David, H. Alia: Petri Nets and Grafcet. Prentice Hall Int. Eles, K. Fengler, A.

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Rozprawy Elektrotechniczne, , T. Dagless, J. Design of Reconfigurable Logic Controllers.

Symbolic Coloring of Petri Nets. Modular Synthesis of Petri Nets. Architectural Synthesis of Petri Nets. Some of the most intuitive designs use a peripheral bus to provide a coprocessor like arrangement for the reconfigurable array. However, there have also been implementations where the reconfigurable fabric is much closer to the processor, some are even implemented into the data path, utilising the processor registers. The job of the host processor is to perform the control functions, configure the logic, schedule data and to provide external interfacing.

The flexibility in reconfigurable devices mainly comes from their routing interconnect. One style of interconnect made popular by FPGAs vendors, Xilinx and Altera are the island style layout, where blocks are arranged in an array with vertical and horizontal routing. A layout with inadequate routing may suffer from poor flexibility and resource utilisation, therefore providing limited performance.

If too much interconnect is provided this requires more transistors than necessary and thus more silicon area, longer wires and more power consumption.

One of the key challenges for reconfigurable computing is to enable higher design productivity and a more easy way to use reconfigurable computing systems for users that are unfamiliar with the underlying concepts. One way of doing this is to provide standardization and abstraction, usually supported and enforced by an operating system.

One of the major tasks of an operating system is to hide the hardware and present programs and their programmers with nice, clean, elegant, and consistent abstractions to work with instead. In other words, the two main tasks of an operating system are abstraction and resource management. Abstraction is a powerful mechanism to handle complex and different hardware tasks in a well-defined and common manner.


One of the most elementary OS abstractions is a process. A process is a running application that has the perception provided by the OS that it is running on its own on the underlying virtual hardware. This can be relaxed by the concept of threads, allowing different tasks to run concurrently on this virtual hardware to exploit task level parallelism.

To allow different processes and threads to coordinate their work, communication and synchronization methods have to be provided by the OS. In addition to abstraction, resource management of the underlying hardware components is necessary because the virtual computers provided to the processes and threads by the operating system need to share available physical resources processors, memory, and devices spatially and temporarily.

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Proceedings of the National Academy of Sciences. A decade of reconfigurable computing: a visionary retrospective. Nebel and A.